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1 for more information www.linear.com/ltc2261-12 typical application features applications description 12-bit, 125/105/80msps ultralow power 1.8v adcs n communications n cellular base stations n software defined radios n portable medical imaging n multi-channel data acquisition n nondestructive testing n 70.8db snr n 85db sfdr n low power: 124mw/103mw/87mw n single 1.8v supply n cmos, ddr cmos or ddr lvds outputs n selectable input ranges: 1v p-p to 2v p-p n 800mhz full-power bandwidth s/h n optional data output randomizer n optional clock duty cycle stabilizer n shutdown and nap modes n serial spi port for configuration n pin compatible 14-bit and 12-bit versions n 40-pin (6mm 6mm) qfn package the lt c ? 2261-12/ltc2260-12/ltc2259-12 are sam - pling 12-bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applications with ac performance that includes 70.8db snr and 85db spurious free dynamic range (sfdr). ultralow jitter of 0.17ps rms allows undersampling of if frequencies with excellent noise performance. dc specs include 0.3lsb inl (typical), 0.1lsb dnl (typical) and no missing codes over temperature. the transition noise is a low 0.3lsb rms . the digital outputs can be either full-rate cmos, double- data rate cmos, or double-data rate lvds . a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single ended with a sine wave, pecl, lvds , ttl or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 2- tone fft , f in = 70mhz and 75mhz ? + input s/h correction logic output drivers 12-bit pipelined adc core clock/duty cycle control d11 ? ? ? d0 125mhz clock analog input 226112 ta01a cmos or lvds 1.2v to 1.8v 1.8v v dd ov dd ognd gnd frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226112 ta01b l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc2261-12 ltc2260-12/ltc2259-12 226112fc
2 for more information www.linear.com/ltc2261-12 absolute maximum ratings supply voltages ( v dd , ov dd ) ....................... C0.3 v to 2 v analog input voltage ( a in + , a in C , par / ser , sense ) ( note 3) .......... C0.3 v to ( v dd + 0.2 v ) digital input voltage ( enc + , enc C , cs , sdi , sck ) ( note 4) .................................... C0.3 v to 3.9 v sdo ( note 4) ............................................. C0.3 v to 3.9 v (notes 1, 2) 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 full-rate cmos output mode top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 a in + a in ? gnd refh refh refl refl par/ser v dd v dd d7 d6 clkout + clkout ? ov dd ognd d5 d4 d3 d2 v dd sense v ref v cm of dnc d11 d10 d9 d8 enc + enc ? cs sck sdi sdo dnc dnc d0 d1 21 30 10 1 t jmax = 150c, ja = 32c/w exposed pad (pin 41) is gnd, must be soldered to pcb 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 double-data rate cmos output mode top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 a in + a in ? gnd refh refh refl refl par/ser v dd v dd d6_7 dnc clkout + clkout ? ov dd ognd d4_5 dnc d2_3 dnc v dd sense v ref v cm of dnc d10_11 dnc d8_9 dnc enc + enc ? cs sck sdi sdo dnc dnc dnc d0_1 21 30 10 1 t jmax = 150c, ja = 32c/w exposed pad (pin 41) is gnd, must be soldered to pcb 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 double-data rate lvds output mode top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 a in + a in ? gnd refh refh refl refl par/ser v dd v dd d6_7 + d6_7 ? clkout + clkout ? ov dd ognd d4_5 + d4_5 ? d2_3 + d2_3 ? v dd sense v ref v cm of + of ? d10_11 + d10_11 ? d8_9 + d8_9 ? enc + enc ? cs sck sdi sdo dnc dnc d0_1 ? d0_1 + 21 30 10 1 t jmax = 150c, ja = 32c/w exposed pad (pin 41) is gnd, must be soldered to pcb pin configurations digital output voltage ................ C0.3 v to ( ov dd + 0.3 v ) operating temperature range : ltc 2261 c , ltc 2260 c , ltc 2259 c ............ 0 c to 70 c ltc 2261 i , ltc 2260 i , ltc 2259 i ........... C40 c to 85 c storage temperature range .................. C65 c to 150 c ltc2261-12 ltc2260-12/ltc2259-12 226112fc
3 for more information www.linear.com/ltc2261-12 converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltc2261-12 ltc2260-12 ltc2259-12 units min typ max min typ max min typ max resolution (no missing codes) l 12 12 12 bits integral linearity error differential analog input (note 6) l C1 0.3 1 C1 0.3 1 C1 0.3 1 lsb differential linearity error differential analog input l C0.4 0.1 0.4 C0.4 0.1 0.4 C0.4 0.1 0.4 lsb offset error (note 7) l C9 1.5 9 C9 1.5 9 C9 1.5 9 mv gain error internal reference external reference l C1.5 1.5 0.4 1.5 C1.5 1.5 0.4 1.5 C1.5 1.5 0.4 1.5 %fs %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm/c ppm/c transition noise external reference 0.3 0.3 0.3 lsb rms order information lead free finish tape and reel part marking* package description temperature range ltc2261cuj-12#pbf ltc2261cuj-12#trpbf ltc2261uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2261iuj-12#pbf ltc2261iuj-12#trpbf ltc2261uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2260cuj-12#pbf ltc2260cuj-12#trpbf ltc2260uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2260iuj-12#pbf ltc2260iuj-12#trpbf ltc2260uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2259cuj-12#pbf ltc2259cuj-12#trpbf ltc2259uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2259iuj-12#pbf ltc2259iuj-12#trpbf ltc2259uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. * the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc2261-12 ltc2260-12/ltc2259-12 226112fc
4 for more information www.linear.com/ltc2261-12 analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 125msps per pin, 105msps per pin, 80msps 155 130 100 a a a i in1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i in2 par /ser input leakage current 0 < par /ser < v dd l C3 3 a i in3 sense input leakage current 0.625v < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.17 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2261-12 ltc2260-12 ltc2259-12 units min typ max min typ max min typ max snr signal-to-noise ratio 5mhz input 70mhz input 140mhz input l 69.4 70.8 70.7 70.4 69.4 70.8 70.7 70.4 69.1 70.6 70.5 70.2 db db db sfdr spurious free dynamic range 2nd or 3rd harmonic 5mhz input 70mhz input 140mhz input l 76 88 85 82 76 88 85 82 79 88 85 82 db db db spurious free dynamic range 4th harmonic or higher 5mhz input 70mhz input 140mhz input l 83 90 90 90 82 90 90 90 85 90 90 90 db db db s/(n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 140mhz input l 68.6 70.6 70.4 70 68.6 70.6 70.4 70 68.8 70.4 70.3 69.9 db db db internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v ltc2261-12 ltc2260-12/ltc2259-12 226112fc
5 for more information www.linear.com/ltc2261-12 digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf digital inputs (cs, sdi, sck) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 4 pf digital d ata outputs (cmos modes: full- d ata rate and double- d ata rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital d ata outputs ( lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
6 for more information www.linear.com/ltc2261-12 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions ltc2261-12 ltc2260-12 ltc2259-12 units min typ max min typ max min typ max cmos output modes: full-data rate and double-data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.9 1.1 1.9 1.1 1.9 v i vdd analog supply current dc input sine wave input l 68.7 70 81.1 57.1 58.3 67.4 48 49 56.6 ma ma i ovdd digital supply current sine wave input, ov dd =1.2v 3.5 2.9 2.2 ma p diss power dissipation dc input sine wave input, ov dd =1.2v l 124 130 146 103 108 122 87 91 102 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.9 1.7 1.9 1.7 1.9 v i vdd analog supply current sine wave input l 73.6 86.9 61.9 73.1 52.7 62.2 ma i ovdd digital supply current (0v dd = 1.8v) sine input, 1.75ma mode sine input, 3.5ma mode l l 18.8 36.7 22.2 43.3 18.8 36.7 22.2 43.3 18.8 36.7 22.2 43.3 ma ma p diss power dissipation sine input, 1.75ma mode sine input, 3.5ma mode l l 166 199 196 235 145 177 172 210 129 161 152 190 mw mw all output modes p sleep sleep mode power 0.5 0.5 0.5 mw p nap nap mode power 9 9 9 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 10 10 10 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2261-12 ltc2260-12 ltc2259-12 units min typ max min typ max min typ max f s sampling frequency (note 10) l 1 125 1 105 1 80 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2.0 4 4 500 500 4.52 2.00 4.76 4.76 500 500 5.93 2.00 6.25 6.25 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 3.8 2.0 4 4 500 500 4.52 2.00 4.76 4.76 500 500 5.93 2.00 6.25 6.25 500 500 ns ns t ap sample-and-hold acquisition delay time 0 0 0 ns symbol parameter conditions min typ max units digital data outputs (cmos modes: full-data rate and double-data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full-data rate mode double-data rate mode 5.0 5.5 cycles cycles ltc2261-12 ltc2260-12/ltc2259-12 226112fc
7 for more information www.linear.com/ltc2261-12 symbol parameter conditions min typ max units digital data outputs ( lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 5.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 125mhz (ltc2261), 105mhz (ltc2260), or 80mhz (ltc2259), lvds outputs with internal termination disabled, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 125mhz (ltc2261), 105mhz (ltc2260), or 80mhz (ltc2259), enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2v p-p with differential drive, 5pf load on each digital output unless otherwise noted. note 10: recommended operating conditions. timing diagrams full-rate cmos output mode timing all outputs are single ended and have cmos levels t h t d t c t l n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + clkout + clkout ? d0-d11, of 226112 td01 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
8 for more information www.linear.com/ltc2261-12 timing diagrams double-data rate cmos output mode timing all outputs are single ended and have cmos levels t h t d ? ? ? t d t c t c t l of n-5 of n-4 of n-3 of n-2 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d0 n-2 d1 n-2 d10 n-5 d11 n-5 d10 n-4 d11 n-4 d10 n-3 d11 n-3 d10 n-2 d11 n-2 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + d0_1 d10_11 clkout + clkout ? of 226112 td02 double-data rate lvds output mode timing all outputs are differential and have lvds levels t h t d t d t c t c t l of n-5 of n-4 of n-3 of n-3 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d1 n-3 d0 n-2 d1 n-2 d10 n-5 d11 n-5 d10 n-4 d11 n-4 d10 n-3 d11 n-3 d10 n-2 d11 n-2 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + d0_1 + d0_1 ? d10_11 + d10_11 ? clkout + clkout ? of + of ? 226112 td03 ? ? ? ltc2261-12 ltc2260-12/ltc2259-12 226112fc
9 for more information www.linear.com/ltc2261-12 timing diagrams a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 226112 td04 cs sck sdi r/w sdo high impedance typical performance characteristics ltc2261-12: integral nonlinearity (inl) ltc2261-12: differential nonlinearity (dnl) ltc2261-12: 8k point fft , f in = 5mhz C1dbfs, 125msps output code 0 ?1.0 ?0.4 ?0.6 ?0.8 inl error (lsb) ?0.2 0 0.2 0.8 0.4 0.6 1.0 1024 2048 3072 4096 226112 g01 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 226112 g02 frequency (mhz) ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 226112 g03 0 10 20 30 40 50 60 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
10 for more information www.linear.com/ltc2261-12 typical performance characteristics ltc2261-12: 8k point fft , f in = 30mhz C1dbfs, 125msps ltc2261-12: 8k point fft , f in = 70mhz C1dbfs, 125msps ltc2261-12: 8k point fft , f in = 140mhz C1dbfs, 125msps ltc2261-12: 8k point 2- tone fft , f in = 70mhz, 75mhz, C1dbfs, 125msps ltc2261-12: shorted input histogram ltc2261-12: sfdr vs input level, f in = 70mhz, 2v range, 125msps ltc2261-12: i vdd vs sample rate, 5 mhz sine wave input, C1db frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 226112 g04 10 20 30 40 50 60 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226112 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226112 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 60 226112 g07 output code 2041 2000 0 10000 8000 6000 4000 count 12000 16000 14000 18000 2043 2045 226112 g08 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226112 g12 dbfs dbc sample rate (msps) 0 75 60 65 70 55 50 80 i vdd (ma) 25 50 75 100 125 226112 g13 lvds outputs cmos outputs input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 226112 g09 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226112 g10 ltc2261-12: sfdr vs input frequency, C1db, 2v range, 125msps ltc2261-12: snr vs input frequency, C1db, 2v range, 125msps ltc2261-12 ltc2260-12/ltc2259-12 226112fc
11 for more information www.linear.com/ltc2261-12 ltc2261-12: i ovdd vs sample rate, 5mhz sine wave input, C1db, 5pf on each data output ltc2261-12: snr vs sense, f in = 5mhz, C1db ltc2260-12: integral nonlinearity ( inl) ltc2260-12: differential nonlinearity ( dnl) ltc2260-12: 8k point fft , f in = 5mhz C1dbfs, 105msps ltc2260-12: 8k point fft , f in = 30mhz C1dbfs, 105msps ltc2260-12: 8k point fft , f in = 70mhz C1dbfs, 105msps ltc2260-12: 8k point fft , f in = 140mhz C1dbfs, 105msps typical performance characteristics sample rate (msps) 0 25 10 15 20 5 0 45 30 35 40 i ovdd (ma) 25 50 75 100 125 226112 g14 1.75ma lvds 1.8v cmos 1.2v cmos 3.5ma lvds sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 226112 g15 output code 0 ?1.0 ?0.4 ?0.6 ?0.8 inl error (lsb) ?0.2 0 0.2 0.4 0.6 0.8 1.0 1024 2048 3072 4096 226112 g21 output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 226112 g22 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226112 g23 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226112 g24 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226112 g25 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226112 g26 sample rate (msps) cmos 0 71 68 69 70 67 72 snr (dbfs) 25 50 75 100 125 226112 g18 ddr cmos lvds ltc2261-12: snr vs sample rate and digital output mode, 30mhz sine wave input, C1db ltc2261-12 ltc2260-12/ltc2259-12 226112fc
12 for more information www.linear.com/ltc2261-12 ltc2260-12: i vdd vs sample rate, 5 mhz sine wave input, C1db ltc2260-12: i ovdd vs sample rate, 5mhz sine wave input, C1db, 5pf on each data output ltc2260-12: snr vs sense, f in = 5mhz, C1db ltc2260-12: shorted input histogram ltc2260-12: sfdr vs input level, f in = 70mhz, 2v range, 105msps typical performance characteristics ltc2259-12: integral nonlinearity ( inl) output code 2044 2000 0 6000 4000 count 8000 16000 14000 12000 10000 18000 2045 2048 226112 g28 sample rate (msps) 0 60 45 50 55 40 65 i vdd (ma) 25 50 75 100 226112 g33 lvds outputs cmos outputs sample rate (msps) 25 10 15 20 5 0 45 30 35 40 i ovdd (ma) 226112 g34 1.75ma lvds 1.8v cmos 1.2v cmos 3.5ma lvds 0 25 50 75 100 input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226112 g32 dbfs dbc sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 226112 g35 output code 0 ?1.0 ?0.4 ?0.6 ?0.8 inl error (lsb) ?0.2 0 0.4 0.6 0.2 0.8 1.0 1024 2048 3072 4096 226112 g41 input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 226112 g29 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226112 g30 ltc2260-12: snr vs input frequency, C1db, 2v range, 105msps ltc2260-12: sfdr vs input frequency, C1db, 2v range, 105msps ltc2260-12: 8k point 2- tone fft , f in = 70mhz, 75mhz, C1dbfs, 105msps frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 50 226112 g27 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
13 for more information www.linear.com/ltc2261-12 typical performance characteristics ltc2259-12: 8k point 2- tone fft , f in = 70mhz, 75mhz, C1dbfs, 80msps ltc2259-12: shorted input histogram ltc2259-12: 8k point fft , f in = 30mhz C1dbfs, 80msps ltc2259-12: 8k point fft , f in = 70mhz C1dbfs, 80msps ltc2259-12: 8k point fft , f in = 140mhz C1dbfs, 80msps ltc2259-12: differential nonlinearity ( dnl) ltc2259-12: 8k point fft , f in = 5mhz C1dbfs, 80msps output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 1024 2048 3072 4096 226112 g42 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226112 g43 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226112 g44 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226112 g45 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226114 g46 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 226114 g47 output code 2052 2000 4000 6000 8000 0 12000 10000 count 14000 16000 18000 2054 2056 226112 g48 input frequency (mhz) 0 72 71 70 69 68 67 66 snr (dbfs) 50 100 150 200 250 300 350 226112 g49 input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 226112 g50 ltc2259-12: snr vs input frequency, C1db, 2v range, 80msps ltc2259-12: sfdr vs input frequency, C1db, 2v range, 80msps ltc2261-12 ltc2260-12/ltc2259-12 226112fc
14 for more information www.linear.com/ltc2261-12 typical performance characteristics ltc2259-12: i vdd vs sample rate, 5 mhz sine wave input, C1db ltc2259-12: i ovdd vs sample rate, 5 mhz sine wave input, C1db, 5pf on each data output ltc2259-12: snr vs sense, f in = 5mhz, C1db sample rate (msps) 0 25 10 15 20 5 0 45 30 35 40 i ovdd (ma) 20 40 60 80 226112 g54 1.75ma lvds 1.8v cmos 1.2v cmos 3.5ma lvds sample rate (msps) 0 50 35 40 45 55 i vdd (ma) 20 40 60 80 226112 g53 lvds outputs cmos outputs sense pin (v) 0.6 71 68 69 70 67 66 72 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1.0 226112 g55 ltc2259-12: sfdr vs input level, f in = 70mhz, 2v range, 80msps input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 226112 g52 dbfs dbc ltc2261-12 ltc2260-12/ltc2259-12 226112fc
15 for more information www.linear.com/ltc2261-12 pin functions pins t hat are the same for all d igital output modes a in + (pin 1): positive differential analog input. a in C (pin 2): negative differential analog input. gnd (pin 3): adc power ground. refh (pins 4, 5): adc high reference. bypass to pins 6, 7 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. refl (pins 6, 7): adc low reference. bypass to pins 4, 5 with a 2.2f ceramic capacitor and to ground with a 0.1f ceramic capacitor. par /ser (pin 8): programming mode selection pin. con - nect to ground to enable the serial programming mode. cs, sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs, sck, sdi become parallel logic inputs that control a reduced set of the a/d operating modes. par /ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v dd (pins 9, 10, 40): 1.8v analog power supply. bypass to ground with 0.1f ceramic capacitors. pins 9 and 10 can share a bypass capacitor. enc + (pin 11): encode input. conversion starts on the rising edge. enc C (pin 12): encode complement input. conversion starts on the falling edge. cs (pin 13): in serial programming mode, ( par /ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode ( par /ser = v dd ), cs controls the clock duty cycle stabilizer. when cs is low, the clock duty cycle stabilizer is turned off. when cs is high, the clock duty cycle stabilizer is turned on. cs can be driven with 1.8v to 3.3v logic. sck (pin 14): in serial programming mode , ( par /ser = 0v), sck is the serial interface clock input. in the parallel programming mode ( par /ser = v dd ), sck controls the digital output mode. when sck is low, the full-rate cmos output mode is enabled. when sck is high, the double- data rate lvds output mode (with 3.5ma output current) is enabled. sck can be driven with 1.8v to 3.3v logic. sdi (pin 15): in serial programming mode, ( par /ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode ( par /ser = v dd ), sdi can be used to power down the part. when sdi is low, the part operates normally. when sdi is high, the part enters sleep mode. sdi can be driven with 1.8v to 3.3v logic. sdo (pin 16): in serial programming mode, ( par /ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v-3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode ( par /ser = v dd ), sdo is not used and should not be connected. ognd (pin 25): output driver ground. ov dd (pin 26): output driver supply. bypass to ground with a 0.1f ceramic capacitor. v cm (pin 37): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 0.1f ceramic capacitor. v ref ( pin 38): reference voltage output . bypass to ground with a 1f ceramic capacitor, nominally 1.25v. sense (pin 39): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . ltc2261-12 ltc2260-12/ltc2259-12 226112fc
16 for more information www.linear.com/ltc2261-12 pin functions full-r ate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d0 to d11 (pins 19-24, 29-34): digital outputs. d11 is the msb. clkout C (pin 27): inverted version of clkout + . clkout + (pin 28): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. dnc (pins 17, 18, 35): do not connect these pins. of (pin 36): over/under flow digital output. of is high when an overflow or underflow has occurred. double-d ata r ate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d0_1 to d10_11 (pins 20, 22, 24, 30, 32, 34): double- data rate digital outputs. tw o data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. clkout C (pin 27): inverted version of clkout + . clkout + (pin 28): data output clock. the digital outputs normally transition at the same time as the falling and ris - ing edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. dnc (pins 17, 18, 19, 21, 23, 29, 31, 33, 35): do not connect these pins. of (pin 36): over/under flow digital output. of is high when an overflow or underflow has occurred. double-d ata r ate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. d0_1 C /d0_1 + to d10_11 C /d10_11 + (pins 19/20, 21/22, 23/24, 29/30, 31/32, 33/34): double-data rate digital outputs. tw o data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11) appear when clkout + is high. clkout C /clkout + (pins 27/28): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of C /of + (pins 35/36): over/under flow digital output. of + is high when an overflow or underflow has occurred . ltc2261-12 ltc2260-12/ltc2259-12 226112fc
17 for more information www.linear.com/ltc2261-12 functional block diagram figure 1. functional block diagram diff ref amp ref buf 2.2f 0.1f 0.1f 0.1f internal clock signals refh refh refl refl clock/duty cycle control range select 1.25v reference first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc ? shift register and correction sdo cs ognd of ov dd d11 clkout ? clkout + d0 226112 f01 input s/h sense v ref a in ? a in + 1f v cm 0.1f v dd /2 third pipelined adc stage output drivers mode control registers sck par/ ser sdi ? ? ? v dd gnd ltc2261-12 ltc2260-12/ltc2259-12 226112fc
18 for more information www.linear.com/ltc2261-12 converter operation the ltc2261-12/ltc2260-12/ltc2259-12 are low power 12-bit 125 msps /105 msps /80 msps a / d converters that are powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially or single ended for lower power consump - tion. the digital outputs can be cmos, double-data rate cmos ( to halve the number of output lines), or double- data rate lvds ( to reduce digital noise in the system.) many additional features can be chosen by programming the mode control registers through a serial spi port. see the serial programming mode section. analog input the analog input is a differential cmos sample-and-hold circuit ( figure 2). the inputs should be driven differentially around a common mode voltage set by the v cm output pin, which is nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v. there should be 180 phase difference between the inputs. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry . figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary . the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line c sample 3.5pf r on 25 r on 25 v dd v dd ltc2261-12 a in + 226112 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm ltc2261-12 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 226112 f03 figure 2. equivalent input circuit figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz applications information ltc2261-12 ltc2260-12/ltc2259-12 226112fc
19 for more information www.linear.com/ltc2261-12 applications information figure 5. recommended front-end circuit for input frequencies from 170mhz to 270mhz figure 6. recommended front-end circuit for input frequencies above 270mhz balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. figure 4. recommended front-end circuit for input frequencies from 70mhz to 170mhz at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driv - ing the a/d. 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 226112 f05 ltc2261-12 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 226112 f04 ltc2261-12 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 226112 f06 ltc2261-12 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
20 for more information www.linear.com/ltc2261-12 applications information 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm ltc2261-12 226112 f07 ? ? + + analog input high speed differential amplifier 0.1f figure 7. front-end circuit using a high speed differential amplifier reference the ltc2261-12/ltc2260-12/ltc2259-12 have an inter - nal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9.) the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.6 ? v sense . v ref refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v 1.25v refl 0.1f 2.2f internal adc high reference buffer 226112 f08 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 1f 0.1f 0.1f ltc2261-12 figure 8. reference circuit sense 1.25v external reference 1f 1f v ref 226112 f09 ltc2261-12 figure 9. using an external 1.25v reference the v ref , refh and refl pins should be bypassed as shown in figure 8. the 0.1f capacitor between refh and refl should be as close to the pins as possible (not on the back side of the circuit board). ltc2261-12 ltc2260-12/ltc2259-12 226112fc
21 for more information www.linear.com/ltc2261-12 applications information encode input the signal quality of the encode inputs strongly affects the a/d noise performance . the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs: the differential encode mode (figure 10) and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu - soidal, pecl or lvds encode inputs (figures 12, 13). the encode inputs are internally biased to 1.2v through 10k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v), and the common mode range is from 1.1v to 1.6v. in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + and enc C should have fast rise and fall times. the single- ended encode mode should be used with cmos encode inputs. to select this mode, enc C is connected to ground and enc + is driven with a square wave encode input. enc + can be taken above v dd ( up to 3.6v) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v. for good jitter performance enc + should have fast rise and fall times. clock duty cycle stabilizer for good performance the encode signal should have a 50%(5%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. the duty cycle stabilizer is enabled by mode control register a 2 (serial programming mode), or by cs (parallel programming mode). v dd ltc2261-12 226112 f10 enc ? enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc ? 226112 f11 0v 1.8v to 3.3v ltc2261-12 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode 100 100 25 d1 enc + enc ? 0.1f 0.1f t1: coilcraft wbc4 - 1wl d1: avago hsms - 2822 resistors, capacitors are 0402 package size 226112 f12 ltc2261-12 t1 1:4 figure 12. sinusoidal encode drive enc + enc ? pecl or lvds clock 0.1f 0.1f 226112 f13 ltc2261-12 figure 13. pecl or lvds encode drive ltc2261-12 ltc2260-12/ltc2259-12 226112fc
22 for more information www.linear.com/ltc2261-12 applications information for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(5%) duty cycle. the duty cycle stabilizer should not be used below 5msps. digital outputs digital output modes the ltc2261-12/ltc2260-12/ltc2259-12 can operate in three digital output modes: full-rate cmos, double- data rate cmos (to halve the number of output lines), or double-data rate lvds (to reduce digital noise in the system). the output mode is set by mode control regis - ter a3 (serial programming mode), or by sck (parallel programming mode). note that double-data rate cmos cannot be selected in the parallel programming mode. full-rate cmos mode in full-rate cmos mode the 12 digital outputs (d0-d11), overflow (of), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. for good performance the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf a digital buffer should be used. double-data rate cmos mode in double- data rate cmos mode, two data bits are multiplexed and output on each data pin. this reduces the number of data lines by seven, simplifying board routing and reducing the number of input pins needed to receive the data. the 6 digital outputs (d0_1, d2_3, d4_5, d6_7, d8_9, d10_11), overflow (of), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. ov dd can range from 1.1v to 1.9v, allowing 1.2v through 1.8v cmos logic outputs. for good performance the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 10pf a digital buffer should be used. when using double-data rate cmos at high sample rates the snr will degrade slightly (see typical performance characteristics section). ddr cmos is not recommended for sample frequencies above 100mhz. double-data rate lvds mode in double- data rate lvds mode, two data bits are multiplexed and output on each differential output pair. there are 6 lvds output pairs (d0_1 + /d0_1 C through d10_11 + /d10_11 C ) for the digital output data. overflow ( of + / of C ) and the data output clock ( clkout + / clkout C ) each have an lvds output pair. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt - age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. in lvds mode, ov dd must be 1.8v. programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by serially programming mode control register a3. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases using just an external 100? termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a3. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is increased by 1.6x to maintain about the same output voltage swing. ltc2261-12 ltc2260-12/ltc2259-12 226112fc
23 for more information www.linear.com/ltc2261-12 overflow bit the overflow output bit (of) outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. phase shifting the output clock in full-rate cmos mode the data output bits normally change at the same time as the falling edge of clkout + , so the rising edge of clkout + can be used to latch the output data. in double-data rate cmos and lvds modes the data output bits normally change at the same time as the falling and rising edges of clkout + . to allow adequate setup-and-hold time when latching the data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. the ltc2261-12/ltc2260-12/ltc2259-12 can also phase shift the clkout + /clkout C signals by serially program - ming mode control register a2. the output clock can be shifted by 0, 45, 90 or 135. to use the phase shifting feature the clock duty cycle stabilizer must be turned on. another control register bit can invert the polarity of clkout + and clkout C , independently of the phase shift. the combination of these two features enables phase shifts of 45 up to 315 (figure 14). d ata format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary . the 2s complement format can be selected by serially program - ming mode control register a4. table 1. output codes vs input voltage a in + C a in C (2v range) of d11-d0 (offset binary) d11-d0 (2s complement) >+1.000000v +0.999512v +0.999024v 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488v 0.000000v C0.000488v C0.000976v 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 C0.999512v C1.000000v ?C1.000000v 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 applications information clkout + d0-d11, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 226112 f14 enc + figure 14. phase shifting clkout ltc2261-12 ltc2260-12/ltc2259-12 226112fc
24 for more information www.linear.com/ltc2261-12 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable . digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer is enabled by serially programming mode control register a4. alternate bit polarity another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits (d1, d3, d5, d7, d9, d11) are inverted before the output buffers. the even bits (d0, d2, d4, d6, d8, d10), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. when there is a very small signal at the input of the a/d that is centered around mid- scale, the digital outputs toggle between mostly 1s and mostly 0s. this simultaneous switching of most of the bits will cause large currents in the ground plane. by inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. to first order, this cancels current flow in the ground plane, reducing the digital noise. applications information clkout clkout of d11/d0 d10/d0 ? ? ? d2/d0 d1/d0 d0 116112 f15 of d11 d10 d2 d1 d0 randomizer on d11 fpga pc board d10 ? ? ? d2 d1 d0 116112 f15 d0 d1/d0 d2/d0 d10/d0 d11/d0 of clkout ltc2261-12 figure 15. functional equivalent of digital output randomizer figure 16. unrandomizing a randomized digital output signal ltc2261-12 ltc2260-12/ltc2259-12 226112fc
25 for more information www.linear.com/ltc2261-12 the digital output is decoded at the receiver by inverting the odd bits (d1, d3, d5, d7, d9, d11). the alternate bit polarity mode is independent of the digital output randomizereither, both or neither function can be on at the same time. when alternate bit polarity mode is on, the data format is offset binary and the 2s complement control bit has no effect. the alternate bit polarity mode is enabled by serially programming mode control register a 4. digital output test patterns to allow in- circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d11-d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1s to all 0s on alternating samples checkerboard: outputs change from 1010101010101 to 0101010101010 on alternating samples the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate-bit-polarity. output disable the digital outputs may be disabled by serially program - ming mode control register a 3. all digital outputs including of and clkout are disabled. the high impedance disabled state is intended for long periods of inactivityit is too slow to multiplex a data bus between multiple converters at full speed. sleep and nap modes the a/d may be placed in sleep or nap modes to conserve power. in sleep mode the entire a/d converter is powered down, resulting in 0.5mw power consumption. sleep mode is enabled by mode control register a1 (serial program - ming mode), or by sdi (parallel programming mode). the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref , refh, and refl. for the suggested values in figure 8, the a/d will stabilize after 2ms. in nap mode the a / d core is powered down while the internal reference circuits stay active, allowing faster wake-up than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on- chip references can settle from the slight temperature shift caused by the change in supply current as the a/d leaves nap mode. nap mode is enabled by mode control register a1 in the serial programming mode. device programming modes the operating modes of the ltc2261-12 can be pro - grammed by either a parallel interface or a simple serial interface . the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par /ser should be tied to v dd . the cs, sck and sdi pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v or 3.3v cmos logic. table 2 shows the modes set by cs, sck and sdi. table 2. parallel programming mode control bits ( par / ser = v dd ) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck digital output mode control bit 0 = full-rate cmos output mode 1 = double-data rate lvds output mode (3.5ma lvds current, internal termination off) sdi power down control bit 0 = normal operation 1 = sleep mode applications information ltc2261-12 ltc2260-12/ltc2259-12 226112fc
26 for more information www.linear.com/ltc2261-12 applications information serial programming mode to use the serial programming mode, par /ser should be tied to ground. the cs, sck, sdi and sdo pins become a serial interface that program the a / d mode control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again. the first bit of the 16-bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be writ - ten to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 3 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is automatically set back to zero. table 3. serial programming mode register map register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h . this bit is automatically set back to zero at the end of the spi write command. the reset register is write only. bits 6-0 unused, dont care bits. register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x pwroff 1 pwroff 0 bits 7-2 unused, dont care bits. bits 1-0 pwroff 1: pwroff0 power down control bits 00 = normal operation 01 = nap mode 10 = not used 11 = sleep mode ltc2261-12 ltc2260-12/ltc2259-12 226112fc
27 for more information www.linear.com/ltc2261-12 register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x clkinv clkphase1 clkphase0 dcs bits 7-4 unused, dont care bits. bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout+/clkoutC delayed by 45 (clock period ? 1/8) 10 = clkout+/clkoutC delayed by 90 (clock period ? 1/4) 11 = clkout+/clkoutC delayed by 135 (clock period ? 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x ilvds 2 ilvds 1 ilvds 0 termon outoff outmode1 outmode0 bit 7 unused, dont care bit. bits 6-4 ilvds 2: ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 3 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 1.6 the current set by ilvds2: ilvds0 bit 2 outoff output disable bit 0 = digital outputs are enabled 1 = digital outputs are disabled and have high output impedance bits 1-0 outmode1:outmode0 digital output mode control bits 00 = full-rate cmos output mode 01 = double-data rate lvds output mode 10 = double-data rate cmos output mode 11 = not used applications information ltc2261-12 ltc2260-12/ltc2259-12 226112fc
28 for more information www.linear.com/ltc2261-12 applications information register a4: d ata format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 x x outtest 2 outtest 1 outtest 0 abp rand twoscomp bit 7-6 unused, dont care bits. bits 5-3 outtest 2: outtest0 digital output test pattern bits 000 = digital output test patterns off 001 = all digital outputs = 0 011 = all digital outputs = 1 101 = checkerboard output pattern. of, d11-d0 alternate between 1 0101 0101 0101 and 0 1010 1010 1010 111 = alternating output pattern. of, d11-d0 alternate between 0 0000 0000 0000 and 1 1111 1111 1111 note: other bit combinations are not used bit 2 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 0 twoscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format note: abp = 1 forces the output format to be offset binary grounding and bypassing the ltc2261-12 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , v ref , refh and refl pins. bypass capacitors must be located as close to the pins as possible. of particular importance is the 0.1f capacitor between refh and refl. this capacitor should be on the same side of the circuit board as the a/d, and as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the larger 2.2f capacitor between refh and refl can be somewhat further away. the v cm capacitor should be located as close to the pin as possible. to make space for this the capacitor on v ref can be further away or on the back of the pc board. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2261-12 is trans - ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance , the exposed pad must be soldered to a large grounded pad on the pc board. ltc2261-12 ltc2260-12/ltc2259-12 226112fc
29 for more information www.linear.com/ltc2261-12 typical applications ain + ain ? gnd refh refh refl refl par/ ser v dd v dd d7 d6 clkout + clkout ? ov dd ognd d5 d4 d3 d2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 r13 100 encode clock spi bus 226112 ta02 c20 2.2f c15 0.1f par/ ser r27 10 r16 100 r28 10 c21 0.1f gnd enc + enc ? cs sck sdi sdo dnc dnc d0 d1 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 v dd sense v ref v cm of + of ? d11 d10 d9 d8 0v dd c37 0.1f ltc2261cuj c23 1f sense c17 1f c13 1f c51 4.7pf r14 1k r39 33.2 1% r40 33.2 1% c12 0.1f r15 100 r10 10 r9 10 analog input t2 mabaes0060 ? ? c19 0.1f c18 0.1f digital outputs digital outputs v dd v dd ltc2261 schematic ltc2261-12 ltc2260-12/ltc2259-12 226112fc
30 for more information www.linear.com/ltc2261-12 typical applications silkscreen top top side inner layer 2 gnd inner layer 3 226112 ta03 226112 ta04 226112 ta05 226112 ta06 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
31 for more information www.linear.com/ltc2261-12 typical applications inner layer 4 inner layer 5 power bottom side 226112 ta07 226112 ta08 226112 ta09 ltc2261-12 ltc2260-12/ltc2259-12 226112fc
32 for more information www.linear.com/ltc2261-12 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 40 39 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) ltc2261-12 ltc2260-12/ltc2259-12 226112fc
33 for more information www.linear.com/ltc2261-12 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 08/12 corrected reset register a0, d7 description. attached v dd to pins 9,10 and 40 on schematic. 26 29 c 01/14 corrected external reference to internal reference for 1v input range. 20 (revision history begins at rev b) ltc2261-12 ltc2260-12/ltc2259-12 226112fc
34 for more information www.linear.com/ltc2261-12 ? linear technology corporation 2008 lt 0114 rev c ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2261-12 related parts part number description comments lt1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/ output amplifier/driver low distortion: C94dbc at 1mhz ltc2215 16-bit, 65msps, low noise adc 700mw, 81.5db snr, 100db sfdr, 64-pin qfn ltc2216 16-bit, 80msps, low noise adc 970mw, 81.3db snr, 100db sfdr, 64-pin qfn ltc2217 16-bit, 105msps, low noise adc 1190mw, 81.2db snr, 100db sfdr, 64-pin qfn ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 140mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2203 16-bit, 25msps, 3.3v adc, lowest noise 220mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2204 16-bit, 40msps, 3.3v adc 480mw, 79db snr, 100db sfdr, 48-pin qfn ltc2205 16-bit, 65msps, 3.3v adc 590mw, 79db snr, 100db sfdr, 48-pin qfn ltc2206 16-bit, 80msps, 3.3v adc 725mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2207 16-bit, 105msps, 3.3v adc 900mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-pin qfn ltc2209 16-bit, 160msps, 3.3v adc, lvds outputs 1450mw, 77.1db snr, 100db sfdr, 64-pin qfn ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64- pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2249 14-bit, 80msps adc 230mw, 73db snr, 5mm 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm 5mm qfn package ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2259-14/ ltc2260-14/ ltc2261-14 14-bit, 80/105/125msps 1.8v adcs, ultra-low power 89mw/106mw/127mw, 73.4db snr, 85db sfdr ddr lvds/ddr cmos/cmos outputs, 6mm 6mm qfn package ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2299 dual 14-bit, 80msps adc 230mw, 71.6db snr, 5mm 5mm qfn package lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports lt5557 400mhz to 3.8ghz high linearity downconverting mixer 23.7dbm iip3 at 2.6ghz, 23.5dbm iip3 at 3.5ghz, nf = 13.2db, 3.3v supply operation, integrated transformer lt5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator integrated rf and lo transformer ltc6400-20 1.8ghz low noise, low distortion differential adc driver for 300mhz if fixed gain 10v/v, 2.1nvhz total input noise, 3mm 3mm qfn-16 package lt6604-2.5/ lt6604 -5/ lt6604-10/ lt6604-15 dual matched 2.5mhz, 5mhz, 10mhz, 15mhz filter with adc driver dual matched 4th order lp filters with differential drivers. low noise, low distortion amplifiers ltc2261-12 ltc2260-12/ltc2259-12 226112fc

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